System-on-chip (SoC) technology integrates multiple functional blocks on a single silicon chip. The multiple functional blocks may include digital circuits, analog circuits, mixed-signal circuits or any combination thereof. SoC technology reduces development cycle and manufacture costs and increases product reliability, functionality and performance.
However, an SoC chip is relatively complicated. Such a complicated chip having various types of functional blocks demands a thorough reliability analysis before going through an expensive and time-consuming fabrication process. Semiconductor aging has emerged as a major factor for SoC chip's reliability. Aging induced defects include Hot Carrier Injection (HCI), which relates to the change in electrons/holes' mobility; Electron-Migration (EM), which relates to the gradual displacement of ions in a conductor as a result of current flowing through the conductor; Negative Bias Temperature Instability (NBTI), which relates to a shift of a threshold voltage of a transistor; and Time Dependent Dielectric Breakdown (TDDB), which relates to the damage caused to the gate oxide region of a transistor. In short, HCI, EM, NBTI and TDDB are major mechanisms of device degradation due to aging effects.
Conventionally, design reliability margin is given by the worst-case assumption. That is, the user usage model of a design is assumed to be operated at high voltage and temperature over expected lifetime. As a result, over design issues in early development stage are incurred. Simulation tools such as Simulation Program with Integrated Circuits Emphasis (SPICE) can be used to simulate aging induced defects.